Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same

ABSTRACT

In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a contact structure wiring line for athin film transistor array substrate, and a method of fabricating thesame.

(b) Description of the Related Art

Generally, a wiring line assembly is formed at a semiconductor device totransmit signals while involving the requirement of minimization insignal delay.

In order to minimize the signal delay, the wiring line assembly isusually formed with a low resistance metallic material such as aluminumand aluminum alloy. However, as the aluminum-based metallic materialinvolves weak physico-chemical characteristic, erosion is liable to bemade at the wiring line assembly when it contacts other conductivematerials at the contact area, and this deteriorates the performancecharacteristics of the semiconductor device. Particularly in the case ofa liquid crystal display, as the pixel electrode is formed with atransparent conductive material such as indium tin oxide (ITO), thealuminum-based layer being in contact with the ITO-based electrode isliable to be eroded. In order to solve such a problem, it has beenproposed that indium zinc oxide (IZO) exhibiting good contactcharacteristic with the aluminum-based metallic material should be usedto form the pixel electrode. However, in this case, the contactresistance becomes increased at the contact area.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a wiring linecontact structure which is formed with a low resistance material whilebearing a low resistance contact characteristic.

It is another object of the present invention to provide a wiring linecontact structure for a thin film transistor array substrate whichinvolves excellent contact characteristic.

These and other objects may be achieved by the following features. Awiring line assembly is formed with an aluminum or aluminum alloy-basedlayer and another conductive layer. The sidewall of the wiring lineassembly is exposed through a contact hole at the contact area, or anopening portion is formed at one of the layers while exposing the otherlayer.

An IZO-based layer is connected to the wiring line assembly through thecontact hole. In order to prevent the IZO-based layer from being cut dueto the stepped difference at the contact area, the distance between theboundary of the contact hole and the boundary of the wiring lineassembly is established to be 2 μm or less.

According to one aspect of the present invention, in a method of forminga wiring line contact structure, a wiring line assembly is formed on asubstrate with a first conductive layer. An insulating layer isdeposited onto the wiring line assembly such that the insulating layercovers the wiring line assembly. The insulating layer is patterned tothereby form a contact hole exposing the sidewall of the wiring lineassembly. A second conductive layer is formed such that the secondconductive layer contacts the sidewall of the wiring line assemblythrough the contact hole.

The first conductive layer is formed with an over-layer based onaluminum or aluminum alloy, and an under-layer based on molybdenum,molybdenum alloy or chrome. The second conductive layer is formed withIZO.

The distance between the boundary of the contact hole and the boundaryof the wiring line assembly is established to be 2 μm or less.

According to another aspect of the present invention, in a method offorming a wiring line contact structure, a wiring line assembly isformed on a substrate such that the wiring line assembly has an openingportion. An insulating layer is deposited onto the substrate such thatthe insulating layer covers the wiring line assembly. The insulatinglayer is patterned to thereby form a contact hole exposing the openingportion. A first conductive layer is formed on the insulating layer suchthat the first conductive layer contacts the wiring line assemblythrough the contact hole.

The wiring line assembly is formed with a second conductive layer havingan over-layer based on aluminum or aluminum alloy, and an under-layerbased on molybdenum, molybdenum alloy or chrome. The first conductivelayer is formed with IZO. The opening portion is formed only at theover-layer while bearing an area of 4×4 μm or less. The over-layer andthe under-layer may be formed through photolithography using onephotoresist pattern.

According to still another aspect of the present invention, a thin filmtransistor array substrate includes a gate line assembly formed on aninsulating substrate. A gate insulating layer covers the gate lineassembly. A semiconductor layer is formed on the gate insulating layer.A data line assembly is formed on the gate insulating layer with thesemiconductor layer. A protective layer covers the data line assembly. Atransparent conductive pattern is formed on the gate insulating layer orthe protective layer. The conductive pattern contacts the sidewall ofthe gate line assembly and the data line assembly through first contactholes formed at the gate insulating layer or the protective layer.

The gate line assembly or the data line assembly is formed with anunder-layer based on chrome, molybdenum or molybdenum alloy, and anover-layer based on aluminum or aluminum alloy. The gate insulatinglayer and the protective layer are formed with silicon nitride. Thetransparent conductive pattern is formed with IZO.

The gate line assembly has gate lines proceeding in the horizontaldirection, gate electrodes connected to the gate lines, and gate padsconnected to the gate lines to receive scanning signals from the outsideand transmit the scanning signals to the gate lines. The data lineassembly has data lines proceeding in the vertical direction, sourceelectrodes connected to the data lines, drain electrodes separated fromthe source electrodes while facing the source electrodes around the gateelectrodes, and data pads connected to the data lines to receive picturesignals from the outside and transmit the picture signals to the datalines. The sidewall of the drain electrodes is exposed through the firstcontact holes.

The protective layer has second contact holes exposing the data pads,and third contact holes exposing the gate pads together with the gateinsulating layer. The area of the first to the third contact holes isestablished to be 4×4 μm-10×10 μm. The transparent conductive pattern isformed with pixel electrodes contacting the sidewall of the drainelectrodes, and subsidiary data and gate pads connected to the data andthe gate pads through the second and the third contact holes. Thesidewall of the data pad or the gate pad is exposed through the secondcontact hole or the third contact hole, and the subsidiary data pad orthe subsidiary data pad contacts the sidewall of the data pad or thegate pad.

In a method of fabricating the thin film transistor array substrate fora liquid crystal display, a gate line assembly is on an insulatingsubstrate. The gate line assembly has gate lines and gate electrodesconnected to the gate lines. A gate insulating layer is deposited ontothe insulating substrate such that the gate insulating layer covers thegate line assembly. A semiconductor layer is formed on the gateinsulating layer. A data line assembly is formed on the gate insulatinglayer with the semiconductor layer. The data line assembly has datalines crossing over the gate lines, source electrodes connected to thedata lines while being positioned close to the gate electrodes, anddrain electrodes facing the source electrodes around the gateelectrodes. A protective layer is deposited onto the substrate, andpatterned to thereby form contact holes exposing the sidewall of thedrain electrodes. Pixel electrodes are formed on the protective layersuch that the pixel electrodes contact the sidewall of the drainelectrodes through the contact holes.

The data line assembly and the semiconductor layer are formed throughphotolithography using a photoresist pattern differentiated inthickness. The photoresist pattern has a first portion with a firstthickness, a second portion with a second thickness greater than thefirst thickness, and a third portion with no thickness.

In the photolithography process, the photoresist pattern is formed usinga photo-mask with a first region bearing a predetermined lighttransmission, a second region bearing a light transmission lower thanthe light transmission of the first region, and a third region bearing alight transmission higher than the light transmission of the firstregion. The first portion of the photoresist pattern is placed betweenthe source and the drain electrodes, and the second portion of thephotoresist pattern is placed over the data line assembly.

The photo-mask has a semitransparent film or a slit pattern bearing aslit width smaller than the light decomposition capacity of the lightexposing device to control the light transmission of the first to thethird regions in a different manner. The thickness of the first portionis established to be ½ or less with respect to the thickness of thesecond portion.

An ohmic contact layer may be formed between the semiconductor layer andthe data line assembly. The data line assembly, the ohmic contact layerand the semiconductor layer are formed using one mask.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings in which likereference symbols indicate the same or the similar components, wherein:

FIGS. 1A to 3E illustrate a wiring line contact structure according tothe present invention;

FIG. 4 is a plan view of a thin film transistor array substrate for aliquid crystal display according to a first preferred embodiment of thepresent invention;

FIG. 5 is a cross sectional view of the thin film transistor arraysubstrate taken along the V-V′ line of FIG. 4;

FIGS. 6A, 7A, 8A and 9A sequentially illustrate the steps of fabricatingthe thin film transistor array substrate shown in FIG. 4;

FIG. 6B is a cross sectional view of the thin film transistor arraysubstrate taken along the VIb-VIb′ line of FIG. 6A;

FIG. 7B is a cross sectional view of the thin film transistor arraysubstrate taken along the VIIb-VIIb′ line of FIG. 7A illustrating theprocessing step following that illustrated in FIG. 6B;

FIG. 8B is a cross sectional view of the thin film transistor arraysubstrate taken along the VIIIb-VIIIb′ line of FIG. 8A illustrating theprocessing step following that illustrated in FIG. 7B;

FIG. 9B is a cross sectional view of the thin film transistor arraysubstrate taken along the IXb-IXb′ line of FIG. 9A illustrating theprocessing step following that illustrated in FIG. 8B;

FIG. 10 is a table illustrating the contact resistance of test patternsformed at the periphery of the thin film transistor array substrateshown in FIG. 4;

FIG. 11 is a plan view of a thin film transistor array substrate for aliquid crystal display according to a second preferred embodiment of thepresent invention;

FIGS. 12 and 13 are cross sectional views of the thin film transistorarray substrate taken along the XII-XII′ line and the XIII-XIII′ line ofFIG. 11;

FIG. 14A illustrates the first step of fabricating the thin filmtransistor array substrate shown in FIG. 11;

FIGS. 14B and 14C are cross sectional views of the thin film transistorarray substrate taken along the XIVb-XIVb′ line and XIVc-XIVc′ line ofFIG. 14A;

FIGS. 15A and 15B illustrate the step of fabricating the thin filmtransistor array substrate following that illustrated in FIGS. 14B and14C;

FIG. 16A illustrates the step of fabricating the thin film transistorarray substrate following that illustrated in FIGS. 15A and 15B;

FIGS. 16B and 16C are cross sectional views of the thin film transistorarray substrate taken along the XVIb-XVIb′ line and the XVIc-XVIc′ lineof FIG. 16A;

FIGS. 17A to 19B sequentially illustrate the steps of fabricating thethin film transistor array substrate following that illustrated in FIGS.16B and 16C;

FIG. 20A illustrates the step of fabricating the thin film transistorarray substrate following that illustrated in FIGS. 19A and 19B; and

FIGS. 20B and 20C are cross sectional views of the thin film transistorarray substrate taken along the XXb-XXb′ line and the XXc-XXc′ line ofFIG. 20A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of this invention will be explained with referenceto the accompanying drawings.

FIGS. 1A to 3E illustrate a wiring line contact structure according tothe present invention. Specifically, FIGS. 1A, 2A, 2C, 3A to 3E are planviews of the wiring line contact structure, and FIGS. 1B, 2B and 2D arecross sectional views of the wiring line contact structure taken alongthe Ib-Ib′ line of FIG. 1A, the IIb-IIb′ line of FIG. 2A, and theIId-IId′ line of FIG. 2C.

In view of minimization in the signal delay, an aluminum or aluminumalloy-based metallic material bearing a low resistivity of 15 μΩcm orless is well adapted for use in forming a signal transmission line for asemiconductor device. The signal transmission line is connected to otherconductive layers to receive the relevant signals and transmit them tothe required place. As the signal transmission line contacts theneighboring conductive layers, the contact resistance should be reducedas much as possible.

For this purpose, as shown in FIGS. 1A and 1B, a first conductive layeris deposited onto a substrate 10 such that it has an under-layer 111bearing a low contact resistance with respect to IZO, such asmolybdenum, molybdenum alloy and chrome, and an over-layer 112 bearing alow resistance, such as aluminum or aluminum alloy, and patterned tothereby form a wiring line assembly 11. An insulating layer 12 is thendeposited onto the substrate 10 such that it covers the wiring lineassembly 11. Thereafter, the insulating layer 12 is patterned such thatit bears a contact hole 13 exposing the wiring line assembly 11. Asecond conductive layer 14 is formed on the insulating layer 12 with IZOsuch that it is directly connected to the wiring line assembly 11through the contact hole 13. The sidewall of the wiring line assembly11, particularly the sidewall of the under-layer 111, is sufficientlyexposed to the outside through the contact hole 13 such that theIZO-based layer 14 contacts the under-layer 111 in a sufficient manner.The contact hole 13 is preferably formed such that the distance dbetween the sidewall of the wiring line assembly 11 exposed through thecontact hole 13 and the sidewall of the contact hole 13 positioned closethereto is established to be 2 μm or less. This is to prevent the secondconductive layer 14 from being cut due to the stepped difference of thecontact hole 13.

Furthermore, as shown in FIGS. 2A and 2B, at least one opening portion15 may be formed at the over-layer 112 of the wiring line assembly 11,and the insulating layer 12 covering the wiring line assembly 11 ispatterned to thereby form a contact hole 13 exposing the opening portion15. Thereafter, a second conductive layer 14 is formed on the insulatinglayer 12 such that it contacts the under-layer 111 of the wiring lineassembly 11 through the opening portion 15. It is preferable that theopening portion 15 is established to bear an area of 4×4 μm or less. Asthe opening portion 15 bears such a small dimension, only one mask maybe used in forming the over-layer 112 and the under-layer 111. That is,when the over-layer 112 and the under-layer 111 differentiated in shapeare patterned, the over-layer 112 is etched using a photoresist patternas an etching mask. Thereafter, the under-layer 601 is etched using theremaining photoresist pattern or the over-layer 602 as an etching mask.As the opening portion 15 bears a small area of 4×4 μm or less, theetching speed becomes slower at the opening portion 15. Therefore, theunder-layer 111 is not completely removed while being partially leftover. In this way, the over-layer 112 and the under-layer 111differentiated in shape can be formed through the photolithographyprocess using one photoresist pattern.

As shown in FIGS. 2C and 2D, the top surface of the under-layer 111 maybe exposed to the outside of the over-layer 112 such that the sidewallof the wiring line assembly bears a stepped structure. This is to securesufficient contact area between the under-layer 111 and the secondconductive layer 14. In order to pattern the over-layer 112 and theunder-layer 111 differentiated in shape using one photoresist pattern, aslit pattern or a semitransparent film may be used. Alternatively, aphotoresist pattern with a relatively thin peripheral portion may beformed through the reflowing process, and etched in a double manner.This will be explained in relation to the process of fabricating a thinfilm transistor array substrate using four masks.

Meanwhile, as shown in FIGS. 3A to 3D, the wiring line assembly 11 andthe contact hole 13 may be transformed in various manner such that theybear a margin for misalignment. As shown in FIG. 3E, plural numbers ofopening portions 15 may be formed at the wiring line assembly 11.

The above wiring line contact structure may be applied for use infabricating a thin film transistor array substrate for a liquid crystaldisplay.

FIG. 4 is a plan view of a thin film transistor array substrate for aliquid crystal display according to a first preferred embodiment of thepresent invention, and FIG. 5 is a cross sectional view of the thin filmtransistor array substrate taken along the V-V′ line of FIG. 4.

A gate line assembly is formed on an insulating substrate 10 with a lowresistance metallic material such as aluminum and aluminum alloy. Thegate line assembly includes gate lines 22 proceeding in the horizontaldirection, gate pads 24 connected to the gate lines 21 to receive gatesignals from the outside and transmit them to the gate lines 22, andgate electrodes 26 connected to the gate lines 22 to form thin filmtransistors together with other electrode components.

A gate insulating layer 30 is formed on the substrate 10 with siliconnitride SiNx while covering the gate line assembly.

A semiconductor layer 40 is formed on the gate insulating layer 30 withamorphous silicon while being placed over the gate electrodes 26 in theshape of an island. Ohmic contact layers 55 and 56 are formed on thesemiconductor layer 40 with n⁺ hydrogenated amorphous silicon wheresilicide or n-type impurities are doped at high concentration.

A data line assembly is formed on the ohmic contact layers 55 and 56 aswell as on the gate insulating layer 30 with a metallic or conductivematerial such as aluminum Al, aluminum alloy, molybdenum Mo,molybdenum-tungsten alloy MoW, chrome Cr, tantalum Ta, and titanium Ti.The data line assembly includes data lines 62 proceeding in the verticaldirection while crossing over the gate lines 22 to define pixel regions,source electrodes 65 branched from the data lines 62 while beingextended over the one-sided ohmic contact layer 54, data pads 68connected to the one-sided ends of the data lines 62 to receive picturesignals from the outside, and drain electrodes 66 separated from thesource electrodes 64 around the gate electrodes 26 while being placed onthe other-sided ohmic contact layer 56.

The data line assembly may be formed with an aluminum or aluminumalloy-based single-layered structure, or a multiple-layered structure.In case the data line assembly is formed with a double-layeredstructure, it is preferable that one layer is formed with a lowresistance material, and the other layer is formed with a materialbearing good contact characteristic with other materials, particularlywith respect to IZO. For instance, Al (or Al alloy)/Cr or Al (or Alalloy)/Mo (or Mo alloy) may be used for that purpose. In this preferredembodiment, the data line assembly is formed with a Cr-based under-layer601 and an aluminum/neodymium (Al/Nd)-based over-layer 602.

A protective layer 70 is formed on the data line assembly and the gateinsulating layer 30 with silicon nitride. Contact holes 76 and 78 areformed at the protective layer 70 while exposing the drain electrodes 66and the data pads 68, respectively. Furthermore, contact holes 74 areformed at the protective layer 70 while exposing the gate pads 24together with the gate insulating layer 30. The boundary of the drainelectrode 66 is exposed through the contact hole 76 such that thesidewalls of the under-layer 601 and the over-layer 602 are exposed tothe outside. The contact hole 76 and the drain electrode 66 may bevaried in shape as shown in FIGS. 3A to 3E. The area of the contact hole76 exposing the drain electrode 66 is preferably established to be 4×4μm-10×10 μm. Furthermore, the boundaries of the pads 24 and 68 may beexposed through the contact holes 74 and 78. In order to minimizecontact resistance at the contact area, the contact holes 74 and 78 arepreferably formed to be larger than the contact hole 76.

Pixel electrodes 82 are formed on the protective layer 70 at therespective pixel regions while being electrically connected to the drainelectrodes 66 through the contact holes 76. The pixel electrodes 82contact the sidewalls of the drain electrodes 66 exposed through thecontact holes 76, particularly the sidewall of the under-layer 601. Inthis structure, the contact resistance at the contact area can beminimized.

Subsidiary gate and data pads 86 and 88 are formed on the protectivelayer 70 while being connected to the gate and the data pads 24 and 68through the contact holes 74 and 78. The pixel electrodes 82, thesubsidiary gate pads 86 and the subsidiary data pads 88 are formed withindium zinc oxide (IZO).

As shown in FIGS. 1 and 2, the pixel electrodes 82 are overlapped withthe gate lines 22 to thereby form storage capacitors. In case thedesired storage capacity is not obtained with the overlapping, a storagecapacitor line assembly may be formed at the same plane as the gate lineassembly.

A method of fabricating the thin film transistor array substrate will benow explained with reference to FIGS. 6A to 9B as well as FIGS. 4 and 5.

As shown in FIGS. 6A and 6B, a conductive layer based on a lowresistance target material such as aluminum/neodymium (Al/Nd) alloycontaining the Nd content of 2 at % is deposited onto a substrate 10through sputtering at 150° C. such that it has a thickness of 2500 Å,and patterned to thereby form a gate line assembly with a taperingstructure. The gate line assembly has gate lines 22, gate electrodes 26,and gate pads 24.

Thereafter, as shown in FIGS. 7A and 7B, a silicon nitride-based gateinsulating layer 30, an amorphous silicon layer 40 and a doped amorphoussilicon layer 50 are sequentially deposited onto the substrate 10, andthe amorphous silicon layer 40 and the doped amorphous silicon layer 50are patterned through photolithography to thereby form a semiconductorlayer 40, and an ohmic contact layer 50 on the gate insulating layer 30over the gate electrodes 24. The gate insulating layer 30 is preferablyformed through depositing a silicon nitride layer at 250-400° C. suchthat it bears a thickness of 2000-5000 Å.

As shown in FIGS. 8A and 8B, an under-layer 601 with a thickness of 500Å based on molybdenum, molybdenum alloy or chrome, and an over-layer 602with a thickness of 2500 Å based on a low resistance target materialsuch as Al—Nd alloy containing the Nd content of 2 at % are sequentiallydeposited onto the substrate 10 through sputtering at 150° C., andpatterned through photolithography to thereby form a data line assemblywith a tapering structure. The data line assembly includes data lines 62crossing over the gate lines 22, source electrodes 65 connected to thedata lines 62 while being extended over the gate electrodes 26, datapads 68 connected to the one-sided ends of the data lines 62, and drainelectrodes 66 facing the source electrodes 65 around the gate electrodes26 while being separated from the source electrodes 65.

The over-layer 602 and the under-layer 601 may be all etched through wetetching. It is also possible that the over-layer 602 is etched throughwet etching whereas the under-layer 601 is etched through dry etching.In case the under-layer 601 is formed with molybdenum or molybdenumalloy, it may be patterned together with the over-layer 602 under thesame etching condition.

An opening portion may be made only at the over-layer 602 of the drainelectrode 66 while forming a contact structure as shown in FIGS. 2A and2B. The area of the opening portion is preferably established to be 4×4μm or less such that a separate photolithography process is not needed.

In order that the under-layer 601 can well contact an IZO-based layer tobe formed later, it is preferable to prevent the under-layer 601 frombeing undercut to the bottom of the over-layer 602, or to extend theunder-layer 601 to the outside of the over-layer 602. In case theunder-layer 601 is formed with molybdenum or molybdenum alloy, thethickness ratio of the under-layer 601 to the over-layer 602 isestablished to be ⅕ or more, and the deposition thereof is made by wayof a DIP mode, thereby preventing the under-layer 601 from beingundercut. Furthermore, in case the under-layer 601 is formed withchrome, the aluminum or aluminum alloy-based over-layer 602 is partiallyremoved during the step of cleaning or removing the photoresist filmsuch that the chrome-based under-layer 601 is exposed to the outside.

Thereafter, the doped amorphous silicon layer 50 exposed through thedata line assembly is etched such that it is separated into two portionsaround the gate electrode 26 while exposing the semiconductor layer 40between them. In order to stabilize the exposed surface of thesemiconductor layer 40, oxygen plasma is preferably made thereto.

As shown in FIGS. 9A and 9B, an inorganic insulating layer based onsilicon nitride is deposited onto the substrate 10 at 250-400° C. tothereby form a protective layer 70. The protective layer 70 is patternedthrough photolithography together with the gate insulating layer 30 tothereby form contact holes 74, 76 and 78 exposing the gate pads 24, thedrain electrodes 66 and the data pads 68, respectively. The etchingcondition is preferably established such that the aluminum or aluminumalloy-based metallic layer is not etched. An F-based gas may be used asthe etching gas. The boundary of the drain electrode 66 is exposedthrough the contact hole 76 such that the sidewalls of the over-layer602 and the under-layer 601 are exposed to the outside. It is preferablethat the boundary of the contact hole 76 and the boundary of the drainelectrode 66 are spaced apart from each other with a distance of 2 μm orless. This is to minimize the contact resistance between the pixelelectrodes 82 and the drain electrodes 66 while preventing the drainelectrodes 66 from being undercut due to the formation of the contactholes 76. That is, when the distance between the boundary of the contacthole 76 and the boundary of the drain electrode 66 is established to be3 μm or more, the gate insulating layer 30 is extremely etched to thebottom of the drain electrode 66 while making undercut at the contacthole 76. Consequently, the pixel electrode 82 to be formed later may becut at the bottom of the drain electrode 66 due to the steppeddifference of the gate insulating layer 30 while increasing the contactresistance at the contact area. However, in this preferred embodiment,as the distance between the boundary of the contact hole 76 and theboundary of the drain electrode 66 is established to be 2 μm or less,the gate insulating layer 30 is not overly etched to the bottom of thedrain electrode 66 while completely exposing the sidewall of the drainelectrode 66. Of course, it is also possible that the boundaries of thepads 24 and 68 may be exposed to the outside through the contact holes74 as shown in FIGS. 1A and 1B.

Finally, as shown in FIGS. 4 and 5, an IZO-based layer is deposited ontothe substrate 10 through sputtering, and patterned throughphotolithography to thereby form pixel electrodes 82 connected to thedrain electrodes 66 through the contact holes 76, and subsidiary gateand data pads 86 and 88 connected to the gate and the data pads 24 and68 through the contact holes 74 and 78, respectively. The pixelelectrodes 82 are prevented from being cut while contacting theunder-layer 601 in a reliable manner, thereby minimizing the contactresistance at the contact area. Indium x-metal oxide (IDIXO) by theIdemitsu Company is used as the target material for forming theIZO-based layer 82, 86 and 88. The target material contains In₂O₃ andZnO. It is preferable that the Zn content is established to be 15-20 at%. In order to minimize the contact resistance, the deposition of theIZO-based layer is made at 250° C. or less.

A contact structure was formed at the periphery of the substrateexternal to the display area thereof as a test pattern such that it borethe same structure as that formed at the display area, and the contactresistance was measured in three possible cases. In the first case, thecontact hole 76 was formed over the drain electrode 66. In the secondcase, the boundary of the contact hole 76 was spaced apart from theboundary of the drain electrode 66 by the distance of 3 μm or more. Inthe third case, the boundary of the contact hole 76 was spaced apartfrom the boundary of the drain electrode 66 by the distance of 2 μm orless. Two hundred test patterns were made in relation to the first tothe third cases, and contact resistance thereof was measured. As aresult, the contact resistance related to the first and the second casesturned out to be E7 Ω or more, but that related to the third case to beE6 Ω or less.

Meanwhile, the contact resistance at the contact area was measured byway of test patterns in relation to various processing conditions.

FIG. 10 is a table illustrating the contact resistance of the testpatterns formed at the periphery of the thin film transistor arraysubstrate.

The test patterns were formed at the periphery of the substrate externalto the display area thereof. As shown in FIGS. 1A and 1B, the contactstructure was simplified with a wiring line assembly bearing achrome-based under-layer and an aluminum alloy-based over-layer, asilicon nitride-based insulating layer with a contact hole, and anIZO-based layer. Two hundred contact structures were made, and thecontact resistance thereof was measured. In the first pattern, theboundary of the contact hole was placed over the wiring line assembly.In the second pattern, the sidewall of the wiring line assemblycontacted the IZO-based layer. The contact resistance of the insulatinglayer was measured in condition that the protective layer and the gateinsulating layer were deposited at 235° C. and 310° C. by the thicknessof 2000 Å and 3000 Å, respectively. The contact resistance of the wiringline assembly was measured in condition that the aluminum alloy-basedlayer was deposited at 150° C. and 50° C., respectively. Furthermore,the contact resistance of the wiring line assembly was measured inseveral different cases. In the first case, the wiring line assembly wasexposed to the gas for etching the ohmic contact layers of 1500 Å and3000 Å. In the second case, the insulating layer was etched by way of aPE mode for 63 seconds and 68 seconds to thereby form contact holes. Inthe third case, the insulating layer was etched by way of an ICP mode at1000W and 400W to thereby form contact holes. In the fourth case, thewiring line assembly exposed through the contact holes was cleaned for70 seconds, or not.

As shown in FIG. 10, when the contact hole is formed by 10×10 μm, thecontact resistance of the first pattern turned out to be 5.3MΩ-4.0GΩ,and that of the second pattern to be 14KΩ-515KΩ. There existed a casewhere the contact resistance of the first pattern was measured to be60KΩ. In this case, the contact structure of the first pattern wasformed like that of the second pattern such that the boundary of thewiring line assembly was exposed through the contact hole, and theIZO-based layer sufficiently contacted the sidewall of the wiring lineassembly, particularly the under-layer thereof.

Furthermore, in case the contact hole was formed by 7×7 μm, the contactresistance of the first pattern turned out to be 12MΩ-7.9GΩ, and that ofthe second pattern to be 18KΩ-664KΩ. In case the contact hole was formedby 4×4 μm, the contact resistance of the first pattern turned out to be48MΩ-85GΩ, and that of the second pattern to be 30KΩ-1.2MΩ.

In the above-structured thin film transistor array substrate, the gateline assembly and the data line assembly contain a low resistanceconductive layer based on aluminum or aluminum alloy, and the contactresistance between the data line assembly and the IZO-based pixelelectrodes 82 at the contact area is minimized. Consequently, such asubstrate can be well adapted for use in fabricating a wide-screenedhigh definition liquid crystal display.

Alternatively, the above process may be made using only four masks.

FIG. 11 is a plan view of a thin film transistor array substrate for aliquid crystal display according to a second preferred embodiment of thepresent invention, and FIGS. 12 and 13 are cross sectional views of thethin film transistor array substrate taken along the XII-XII′ line andthe XIII-XIII′ line of FIG. 11.

A gate line assembly is formed on an insulating substrate 10 with a lowresistance conductive material such as aluminum and aluminum alloy. Thegate line assembly includes gate lines 22, gate pads 24, and gateelectrodes 26. The gate line assembly further includes storage capacitorelectrodes 28 proceeding parallel to the gate lines 22 to receive commonelectrode voltages from the outside. The storage capacitor electrodes 28are overlapped with storage capacitor conductive patterns 68 connectedto pixel electrodes 82 to thereby form storage capacitors for enhancingthe electric potential storage capacity of the pixels. In case thedesired storage capacity is obtained with the overlapping of the pixelelectrodes 82 and the gate lines 22, the storage capacitor electrodes 28may be omitted.

The gate line assembly may bear a double-layered structure. In thiscase, the gate line assembly has an under-layer 201 based on chrome,molybdenum, molybdenum alloy, tantalum or titanium, which exhibits a lowcontact resistance with respect to IZO, and an over-layer 202 based onaluminum or aluminum alloy.

A gate insulating layer 30 is formed on the gate line assembly withsilicon nitride SiNx while covering the gate line assembly.

Semiconductor patterns 42 and 48 are formed on the gate insulating layer30 with hydrogenated amorphous silicon. Ohmic contact patterns 55, 56and 58 are formed on the semiconductor patterns 42 and 48 with amorphoussilicon where n type impurities such as phosphorous P are doped at highconcentration.

A data line assembly is formed on the ohmic contact patterns 55, 56 and58 with a low resistance conductive material such as aluminum andaluminum alloy. The data line assembly includes a data line unit withdata lines 62 proceeding in the vertical direction, data pads 68connected to the one-sided ends of the data lines 62 to receive picturesignals from the outside, and source electrodes 65 branched from thedata lines 62. The data line assembly further includes drain electrodes66 facing the source electrodes 65 around the gate electrodes 26 or thechannel portions C while being separated from the source electrodes 65,and storage capacitor conductive patterns 64 placed over the storagecapacitor electrodes 28. In case the storage capacitor electrodes 28 areabsent, the storage capacitor conductive patterns 64 are also omitted.

The data line assembly may bear a double-layered structure. In thiscase, the gate line assembly has an under-layer 601 based on chrome,molybdenum, molybdenum alloy, tantalum or titanium, and an over-layer602 based on aluminum or aluminum alloy.

The ohmic contact patterns 55, 56 and 58 lower the contact resistancebetween the semiconductor patterns 42 and 48 and the data line assemblywhile bearing the same shape as the data line assembly. That is, thedata line unit ohmic contact pattern 55 has the same shape as the dataline unit 62, 65 and 68, and the drain electrode ohmic contact pattern56 has the same shape as the drain electrode 66, and the storagecapacitor ohmic contact pattern 58 has the same shape as the storagecapacitor conductive pattern 64.

Meanwhile, the semiconductor patterns 42 and 48 have the same shape asthe data line assembly and the ohmic contact patterns 55, 56 and 58except for the channel portions C. Specifically, the storage capacitorsemiconductor pattern 48, the storage capacitor conductive pattern 64and the storage capacitor ohmic contact pattern 58 have the same shape,but the thin film transistor semiconductor pattern 42 slightly differsfrom the data line assembly and the ohmic contact patterns. That is, thesource and the drain electrodes 65 and 66 are separated from each otherat the channel portion C, and the data line unit ohmic contact pattern55 and the drain electrode ohmic contact pattern 56 are also separatedfrom each other at the channel portion C. However, the thin filmtransistor semiconductor pattern 42 continuously proceeds at the channelportion C without separation to thereby form a thin film transistorchannel.

A protective layer 70 is formed on the data line assembly with siliconnitride.

The protective layer 70 has contact holes 76, 78 and 72 exposing thedrain electrodes 66, the data pads 68, and the storage capacitorconductive patterns 64, respectively. Furthermore, the protective layer70 has contact holes 74 exposing the gate pads 24 together with the gateinsulating layer 30. The contact holes 72, 74, 76 and 78 are formed suchthat they expose the sidewalls of the storage capacitor conductivepatterns 64, the gate pads 24, the drain electrodes 66 and the data pads68, particularly the under-layers 201 and 601 thereof, which exhibit alow contact resistance with respect to the IZO-based layer.

Pixel electrodes 82 are formed on the protective layer 70 to receivepicture signals from the thin film transistors and form electric fieldstogether with a common electrode formed at the counter substrate. Thepixel electrodes 82 are formed with a transparent conductive materialsuch as indium zinc oxide (IZO). The pixel electrodes 82 areelectrically connected to the drain electrodes 66 through the contactholes 76 to receive the picture signals. Furthermore, the pixelelectrodes 82 are overlapped with the neighboring gate lines 22 and datalines 62 to enhance the opening or aperture ratio. The overlapping maybe omitted. In addition, the pixel electrodes 82 are connected to thestorage capacitor conductive patterns 64 through the contact holes 72 totransmit the picture signals to the conductive patterns 64. Subsidiarygate and data pads 86 and 88 are formed over the gate and the data pads24 and 68 while being connected thereto through the contact holes 74 and78 to reinforce the adhesive strength of the pads 24 and 68 to externalcircuits while protecting the pads. The subsidiary gate and data pads 84and 88 are not necessary, but may be selectively introduced. TheIZO-based layers 82, 86 and 88 contact the sidewalls of the storagecapacitor conductive patterns 64, the gate pads 24, the drain electrodes66 and the data pads 68, particularly the under-layers 201 and 601thereof exhibiting a lower contact resistance with respect to theIZO-based layer.

It is possible that the pixel electrodes are formed with a transparentconductive polymer. In the case of a reflective type liquid crystaldisplay, the pixel electrodes 82 may be formed with an opaque conductivematerial.

A method of fabricating the thin film transistor array substrate will benow explained with reference to FIGS. 14A to 21C as well as FIGS. 11 to13.

As shown in FIGS. 14A to 14C, an under-layer 201 based on molybdenum,molybdenum alloy or chrome, which exhibits a contact resistance withrespect to IZO lower than aluminum, and an over-layer 202 based on Al—Ndalloy containing the Nd content of 2 at % are sequentially depositedonto a substrate 10 through sputtering, and patterned throughphotolithography using a mask to thereby form a gate line assemblybearing a tapering structure. The gate line assembly has gate lines 22,gate pads 24, gate electrodes 26, and storage capacitor electrodes 28.In order that the under-layer 201 can contact an IZO-based layer to beformed later in a sufficient manner, the under-layer 201 is preventedfrom being undercut to the bottom of the over-layer 202, or extends tothe outside of the over-layer 202. For this purpose, in case theunder-layer 201 is formed with molybdenum or molybdenum alloy, thethickness ratio of the under-layer 201 to the over-layer 202 isestablished to be ⅕ or more, and the etching thereof is made by way of aDIP mode where the substrate is dipped in the etching solution such thatthe under-layer 201 can be prevented from being undercut. Furthermore,in case the under-layer 201 is formed with chrome, the under-layer 201is deposited by the thickness of 500 Å or less, and the aluminum oraluminum alloy-based over-layer is partially removed during the cleaningprocess or the photoresist film removal process. In this way, thechrome-based under-layer 201 extends to the outside of the over-layer202.

Thereafter, as shown in FIGS. 15A and 15B, a gate insulating layer 30, asemiconductor layer 40 and an ohmic contact layer 50 are sequentiallydeposited onto the substrate 10 by way of chemical vapor deposition suchthat they bear a thickness of 1500-5000 Å, 500-2000 Å and 300-600 Å,respectively. A conductive layer 60 with an under-layer 601 based onaluminum or aluminum alloy and an over-layer 602 based on chrome,molybdenum or molybdenum alloy is deposited onto the substrate 10 by wayof sputtering such that it bears a thickness of 1500-3000 Å. Aphotoresist film 110 with a thickness of 1-2 μm is then coated onto theconductive layer 60.

As shown in FIGS. 16B and 16C, the photoresist film 110 is then exposedto light through a second mask, and developed to thereby form aphotoresist pattern with first and second pattern portions 114 and 112.The first photoresist pattern portion 114 is placed at the channel areaC between the source and the drain electrodes 65 and 66, and the secondphotoresist pattern portion 112 is placed at the data line assembly areaA. The first photoresist pattern portion 114 is established to bear athickness smaller than that of the second photoresist pattern portion112. The photoresist film portion at the remaining area B is allremoved. The thickness ratio of the first photoresist pattern portion114 to the second photoresist pattern portion 112 should be controlledto be varied depending upon the etching conditions at the subsequentprocessing steps. It is preferable that the thickness of the firstphotoresist pattern portion 114 should be established to be ½ or less ofthe thickness of the second photoresist pattern portion 112, forinstance to be 4000 Å or less.

In order to differentiate the thickness of the photoresist film, asemi-transmission region may be formed at the mask with a slit orlattice pattern or a semitransparent film.

It is preferable that the patterning width should be smaller than thelight decomposition capacity of the light exposing device. In the caseof using the semitransparent film, thin films differentiated in thelight transmission or the thickness may be used to control the lighttransmission in the fabrication of a mask.

When a photoresist film is exposed to light using such a mask, the highmolecules at the portion of the photoresist film directly exposed tolight are entirely decomposed, those at the portion of the photoresistfilm with a slit pattern or a semitransparent film are decomposed atsome degree, and those at the portion of the photoresist filmintercepted by a light interception film are not nearly decomposed. Whenthe photoresist film is developed, only the portions of the photoresistfilm where the high molecules are not decomposed are left over whilebeing differentiated in thickness depending upon the moleculardecomposition degree. In case the light exposing time is too long, allof the molecules are liable to be decomposed.

Such a photoresist film 114 with a relatively thin thickness may beformed using a material capable of making re-flow. In this case, thetarget film is exposed to light using a usual mask with a lighttransmission region and a light interception region, and developed. Thefilm portion is partially re-flown to the non-film portion.

Thereafter, the photoresist pattern 114, and the underlying conductivelayer 60, ohmic contact layer 50 and semiconductor layer 40 are etched.At this time, the data line assembly and the underlying layers are leftover at the data line assembly area A, only the semiconductor layer isleft over at the channel area C, and all of the conductive layer 60, theohmic contact layer 50 and the semiconductor layer 40 are removed at theremaining area B while exposing the gate insulating layer 30 to theoutside.

Specifically, as shown in FIGS. 14A and 14B, the conductive layer 60exposed at the B area is removed while exposing the underlying ohmiccontact layer 50. In this process, either dry etching or wet etching maybe used in condition that the conductive layer 60 is etched while notnearly etching the photoresist patterns 112 and 114. However, in thecase of the dry etching, it is difficult to find a condition in thatonly the conductive layer 60 is etched while not etching the photoresistpatterns 112 and 114. Therefore, it may be established that thephotoresist patterns 112 and 114 be etched together. In this case, thethickness of the first photoresist pattern portion 114 should beestablished so large as to prevent the underlying conductive layer 60from being exposed to the outside through the etching.

In case the conductive layer 60 contains Mo, MoW alloy, Al, Al alloy orTa, either dry etching or wet etching may be used. However, in the caseof Cr, as it is not well removed through the dry etching, wet etching ispreferably made with respect to the chrome-based layer while usingCeNHO₃ as an etching solution. In case the conductive layer 60 is formedwith Mo or MoW through the dry etching, a mixture of CF₄ and HCl or CF₄and O₂ may be used for the etching gas. In the latter case, the etchingratios thereof with respect to the photoresist film are nearly similarto each other.

Consequently, as shown in FIGS. 17A and 17B, the source/drain conductivepattern 67 and the storage capacitor conductive pattern 64 are left overat the channel area C and the data line assembly area A, and theconductive layer 60 at the remaining area B is all removed whileexposing the underlying ohmic contact layer 50. The conductive patterns67 and 64 have the same shape as the data line assembly except that thesource and the drain electrodes 65 and 66 are connected to each otherwithout separation. Furthermore, in the case of using the dry etching,the photoresist patterns 112 and 114 are also etched by a predeterminedthickness.

Thereafter, as shown in FIGS. 18A and 18B, the ohmic contact layer 50exposed at the B area and the underlying semiconductor layer 40 aresimultaneously removed through dry etching together with the firstphotoresist pattern portion 114. The etching with respect to the ohmiccontact layer 50 and the semiconductor layer 40 should be made incondition that the photoresist patterns 112 and 114, the ohmic contactlayer 50 and the semiconductor layer 40 (the semiconductor layer and theohmic contact layer having no etching selectivity) are simultaneouslyetched while not etching the gate insulating layer 30. Particularly, theetching ratios with respect to the photoresist patterns 112 and 114 andthe semiconductor layer 40 are preferably established to be the same.For instance, the two layers may be etched by nearly the same thicknessusing a mixture of SF₆ and HCl or SF₆ and O₂ as the etching gas. In casethe etching ratios with respect to the photoresist patterns 112 and 114and the semiconductor layer 40 are the same, the thickness of the firstphotoresist pattern portion 114 should be the same as, or less than thesum in thickness of the semiconductor layer 40 and the ohmic contactlayer 50.

Consequently, as shown in FIGS. 18A and 18B, the first photoresistpattern portion 114 at the channel area C is removed while exposing thesource/drain conductive pattern 67, and the ohmic contact layer 50 andthe semiconductor layer 40 at the B area are removed while exposing theunderlying gate insulating layer 30 to the outside. Meanwhile, thesecond photoresist pattern portion 112 at the data line assembly area Ais also etched while being reduced in thickness. In this processingstep, semiconductor patterns 42 and 48 are completed. Reference numerals57 and 58 indicate the ohmic contact patterns under the source/drainconductive pattern 67 and the storage capacitor conductive pattern 64,respectively.

The photoresist film residue remained on the surface of the source/drainconductive pattern 67 at the channel area C is removed through ashing.

Thereafter, as shown in FIGS. 19A and 19B, the source/drain conductivepattern 67 at the channel area C and the underlying source/drain ohmiccontact pattern 57 are removed through etching. Dry etching may be madewith respect to both of the source/drain conductive pattern 67 and theohmic contact pattern 57. Wet etching may be made with respect to thesource/drain conductive pattern 67 while applying the dry etching to theohmic contact pattern 57. In the former case, the etching is preferablymade in condition that the etching selection ratio with respect to thesource/drain conductive pattern 67 and the ohmic contact pattern 57 isgreat. In case the etching selection ratio is not great, it becomesdifficult to find the final point of etching so that the thickness ofthe semiconductor pattern 42 to be left over at the channel area Ccannot be easily controlled. For instance, the source/drain conductivepattern 67 may be etched using a mixture of SF₆ and O₂ as an etchinggas. In the latter case where the wet etching and the dry etching arealternated, the lateral side of the source/drain conductive pattern 67suffering the wet etching is removed, but that of the ohmic contactpattern 57 suffering the dry etching is not nearly etched so that astepped portion is made there. For instance, the ohmic contact pattern57 and the semiconductor pattern 42 may be etched using a mixture of CF₄and HCl or CF₄ and O₂ as the etching gas. In case the mixture of CF₄ andO₂ is used as the etching gas, the semiconductor pattern 42 may bear auniform thickness. At this time, as shown in FIG. 19B, the semiconductorpattern 42 is partially removed while being reduced in thickness, andthe second photoresist pattern portion 112 is etched by a predeterminedthickness. The etching should be made in condition that the gateinsulating layer 30 is not etched. The photoresist film should be sothick as to prevent the second photoresist pattern portion 112 frombeing etched while exposing the underlying data line assembly.

Consequently, the source and the drain electrodes 65 and 66 areseparated from each other while completing the data line assembly andthe underlying ohmic contact patterns 55, 56 and 58.

Finally, the second photoresist pattern portion 112 remained at the dataline assembly area A is removed. However, the removal of the secondphotoresist pattern portion 112 may be made after the source/drainconductive pattern 67 at the channel area C is removed but before theremoval of the underlying ohmic contact pattern 57.

As described above, the wet etching and the dray etching may bealternated, or only the dry etching may be used. In the latter case, theprocessing steps are simplified but it is difficult to find the suitableetching conditions. By contrast, in the former case, it is relativelyeasy to find the suitable etching conditions but the processing stepsare complicated.

After the data line assembly is formed, as shown in FIGS. 20A and 20B, asilicon nitride layer is deposited through CVD at 250-400° C. to therebyform a protective layer 70. The protective layer 70 is etched togetherwith the gate insulating layer 30 using a third mask, thereby formingcontact holes 76, 74, 78 and 72 exposing the under-layers 201 and 601 ofthe drain electrodes 66, the gate pads 24, the data pads 68, and thestorage capacitor conductive patterns 64.

Finally, as shown in FIGS. 11 to 13, an IZO-based layer is depositedonto the substrate 10 through sputtering such that it bears a thicknessof 400-500 Å. The IZO-based layer is etched using a fourth mask tothereby form pixel electrodes 82 connected to the drain electrodes 66and the storage capacitor conductive patterns 64, subsidiary gate pads84 connected to the gate pads 24, and subsidiary data pads 88 connectedto the data pads 68. The etching solution for patterning thechrome-based layer may be used for patterning the IZO-based layer whilepreventing the data line assembly or the gate line assembly from beingeroded. HNO₃/(NH₄)₂Ce(NO₃)₆/H₂O may be used for the etching solution.

In this preferred embodiment, the data line assembly and the underlyingohmic contact patterns 55, 56 and 58 and semiconductor patterns 42 and48 are formed using one mask. In this process, the source and the drainelectrodes 65 and 66 are separated from each other. In this way, theprocessing steps can be simplified.

Alternatively, the contact structure illustrated with reference to FIGS.2A to 3E may be also well applied for use in fabricating the thin filmtransistor array substrates according the first and the second preferredembodiments. Furthermore, the contact structure illustrated withreference to FIGS. 1A to 3E may be also applied for use in fabricatingsemiconductor devices with different structures.

As described above, the sidewall of the wiring line assembly at thecontact area is exposed to the outside, and the conductive layercontacting the IZO-based layer is established to bear a low contactresistance. In this way, the contact resistance between the wiring lineassembly and the IZO-base layer is minimized while ensuring reliabilityat the contact area. Furthermore, as the wiring line assembly contains alow resistance aluminum or aluminum alloy-based conductive layer, it canbe well adapted for use in the wide-screened high definition displaydevice. In addition, the processing steps are simplified while reducingthe production cost.

While the present invention has been described in detail with referenceto the preferred embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A method of forming a wiring line contact structure, the methodcomprising: forming a wiring line assembly having a first a conductivelayer on a surface of a substrate, wherein the first conductive layerhas at least two layers having the same planar shape and a sidewall thatis inclined relative to the surface; depositing an insulating layer ontothe wiring line assembly such that the insulating layer covers thewiring line assembly; patterning the insulating layer to thereby form acontact hole exposing the sidewall of the wiring line assembly; and,forming a second conductive layer such that the second conductive layercontacts the sidewall of the wiring line assembly through the contacthole.
 2. The method of claim 1, wherein the first conductive layer isformed with an over-layer based on aluminum or aluminum alloy, and anunder-layer based on molybdenum, molybdenum alloy or chrome.
 3. Themethod of claim 1, wherein the distance between the boundary of thecontact hole and the boundary of the wiring line assembly is establishedto be 2 μm or less.
 4. The method of claim 1, wherein the secondconductive layer is formed with a transparent conductive material. 5.The method of claim 4, wherein the transparent conductive material isindium zinc oxide (IZO).
 6. A wiring line contact structure, comprising:a wiring line assembly formed on a surface of a substrate, wherein thewiring line assembly has at least two conductive layers having the sameplanar share and a sidewall that is inclined relative to the surface; aninsulating layer covering the wiring line assembly, the insulating layerhaving a contact hole exposing the sidewall of the wiring line assembly;and, a conductive layer formed on the insulating layer with IZO whilecontacting the sidewall of the wiring line assembly through the contacthole.
 7. The wiring line contact structure of claim 6, wherein thewiring line assembly is formed with an under-layer based on chrome,molybdenum or molybdenum alloy, and an over-layer based on aluminum oraluminum alloy.